1. Field of the Invention
The present invention relates to a test key arrangement, and more particularly, to a test key for checking the diffusion window and a method of using the test key.
2. Description of the Prior Art
In semiconductor fabrication, a semiconductor device or an integrated circuit (IC) should be continuously tested in every step so as to maintain device quality and to increase product yield in mass production. Normally, various types of a testing circuit, which is also referred to as “test key”, are simultaneously fabricated with an actual device so that the quality of the actual device can be judged by the performance of the testing circuit or the defects in various component parts due to unexpected processing errors can be found. Once a defective component is found, causes of failure can be investigated and later rectified. The quality of the actual device therefore can be well controlled.
A typical method to test a wafer is called a wafer acceptance testing (WAT) method, which can measure defects of in a wafer. The WAT method includes providing several test keys distributed in a periphery region of a die that is desired to be tested. The test keys typically are formed on a scribe line between dies, and are electrically coupled to an external terminal through a metal pad. A module of the test keys is selected and each test key of the selected module is respectively used for a test of different property of the wafer, such as threshold voltage (VT) or saturate current (IDSAT). A controlled bias is applied to the test keys, and the induced current is read out to detect defects on the wafer.
As the semiconductor integration processes turn more and more complicated, test keys are employed more and more often as well. It is therefore important to improve the accuracy of tests.